The storage capacity of solid state drives (SSDs) continues to increase. That is, SSDs are able to support an ever-increasing number of storage units, such as NAND flash memory units. As storage capacity of SSDs increases, it has become increasingly difficult to scale SSD controllers, which are typically implemented on integrated circuit chips, and which are used to write data to NAND flash memory units and to read data from NAND flash memory units through general-purpose input/output (or GPIO) pins and chip enable (or CE) pins.
With an increasing number of NAND flash memory units supported by present-day disks (greater than 2 terabytes of storage capacity), a greater number of connections from SSD controllers to the NAND flash memory units is required. However, allocating more GPIO and CE pins has a disadvantage because allocating more pins would increase the size of the die package required for the manufacture of the SSD controller. Thus, the cost of manufacturing the SSD controller would increase dramatically. Further, laying out an SSD integrated circuit comprising additional NAND flash memory pin connections would also be costly and disruptive to current SSD controller manufacturing processes. Hence, it would be advantageous to provide a mechanism whereby existing SSD controllers can support disks that have NAND flash memory capacity in excess of 2 terabytes.